Technique for underfilling stacked chips on a cavity MLC module

ABSTRACT

An electronic device is provided comprising a stacked integrated circuit chip assembly wherein the top chip of the assembly is solder connected to the surface of an interconnection substrate with the other chips of the assembly being enclosed in a cavity in the interconnection substrate wherein the cavity and electrical connections of the assembly and between the substrate and top chip are sealed by supplying an encapsulant to the cavity through a through opening in the substrate which communicates with the cavity.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to chip containing electronicdevices and, in particular, to electronic devices containing an assemblyof a plurality of electrically connected stacked chips wherein typicallya larger top chip of the assembly is electrically connected to amulti-layer ceramic (MLC) cavity substrate and a smaller lower chip orchips of the assembly are enclosed in the cavity of the substrate and toa method of their manufacture.

[0003] 2. Description of Related Art

[0004] Electronic components utilizing integrated circuit chips are usedin a number of applications. Controlled Collapse Chip Connection is aninterconnect technology developed by IBM as alternative to wire bonding.This technology is generally known as C4 technology or flip chippackaging. Broadly stated, one or more integrated circuit chips aremounted above a single or multi-layer substrate and pads on each chipare electrically connected to corresponding pads on the substrate by aplurality of electrical connections such as solder bumps. The integratedcircuit chips may be assembled on the substrate in a solder bump arraysuch as a 10×10 array. The chip containing substrate is then typicallyelectrically connected to another electronic device such as a circuitboard by pin connectors with the total package being used in anelectronic device such as a computer.

[0005] Flip chip packaging is described in U.S. Pat. No. 5,191,404 whichpatent is hereby incorporated by reference. In general, flip chipjoining is desirable for many applications because the footprint or arearequired to bond the chip to the substrate is equal to the area of thechip itself. Flip chip joining also exploits the use of a relativelysmall solder bump which typically measures a height of approximately 1mil to 1.5 mils and a width of approximately 2 to 4 mils to join thepads on the chip to corresponding pads on the substrate. Electrical andmechanical interconnects are formed simultaneously by reflowing thebumps at an elevated temperature. The C4 joining process isself-aligning in that the wetting action of the solder will align thechip's bump pattern to the corresponding substrate pads. This actioncompensates for chip to substrate misalignment up to several mils whichmay be incurred during chip placement.

[0006] In the joined flip chip package there is necessarily an openingor space between the pad containing surface of the integrated circuitchip and the pad containing surface of the joined substrate resultingfrom the thickness of the pads on each surface and the solder bumpconnection between the pads. This open space can not be toleratedbecause any interference with the solder connections will adverselyaffect the performance of the package. For example, moisture, theinfusion of thermal paste used to increase heat transfer from the chipand the mechanical integrity of the chip due to the possible breaking ofthe solder bump electrical connections are all serious problems. Tosolve these problems, the solder bumps of the joined integrated circuitchips and substrate are typically encapsulated totally or a sealant isused around the chip edges to seal the joined opening.

[0007] The encapsulation of integrated circuit chips bonded tosubstrates to improve their reliability is well known. For non C-4joining, chips wire bonded or tap bonded are typically completelyencapsulated in a transfer molded thermoset or thermoplastic polymer.Basically, this process involves melting the polymer in a cavity withinthe mold. A plunger then rams the molten polymer through an orifice intothe mold ventricle. The integrated circuit chip and substrate are bondedto each other using a polymeric adhesive and the package is placed inthe mold and the molten polymer forces in and around the package tototally encapsulate the device.

[0008] Flip chip bonding offers many advantages in electronicsmanufacture compared to the complete encapsulation techniques above andone of the most important is the ability to remove and replace the chipwithout scrapping the substrate. This removal of the chip by heating andlifting of the chip from the substrate and replacement with typically anew chip is termed rework and can be performed numerous times withoutdegrading the quality or reliability of the reworked electroniccomponent.

[0009] Encapsulation of the flip chip packages however presents reworkand other problems. The flip chip package must also be reliable andthermal mismatches between the encapsulant, chip, substrate and/orsolder bumps must be minimized to avoid stressing and damaging of thepackage. The encapsulant must also be able to be heated and softened forthe lift-off procedure.

[0010] Recent developments in electronic component fabrication nowprovide components utilizing an assembly of stacked chips, instead of asingle chip, mounted to a substrate. In general, a plurality of chipsare C-4 bonded in a stack assembly resulting in corresponding spacesbetween each of the bonded chips. Typically, the chips are of about thesame size (width and length and surface area) and are mounted to a topchip having a larger width and length and surface area which larger chiphas peripheral non-bonded pads and forms the top of the stackedassembly. Once the chips are joined in the assembly, the peripheralnon-bonded pads of the top chip of the stacked assembly are then C4joined to an MLC substrate. This substrate has a cavity to accommodatethe smaller connected stacked chips and the uppermost top stacked chipoverlies the periphery of the cavity. The peripheral non-bonded C4 bumpson the top chip are then C4 bonded to the surface of the substrate withthe smaller stacked chips being positioned and enclosed in the cavity.

[0011] The conventional chip underfill process to encapsulate the spacebetween a single chip bonded to a non-cavity substrate surface typicallypositions the bonded chip above the top of the substrate and thenapplies the underfill material to the substrate adjacent to theperiphery of the chip to be underfilled. Capillary action draws theunderfill encapsulated material into the space between the chip and thesubstrate to form a void free filled space between the chip and thesubstrate. This technique works very well for a single chip attached tothe surface of a substrate but is not reliable for stacked chipassemblies wherein the stacked chips are enclosed in a cavity of asubstrate.

[0012] Bearing in mind the problems and deficiencies of the prior art,it is therefore an object of the present invention to provide a stackedintegrated circuit chip assembly comprising a plurality of electricallyconnected chips with the chip assembly being electrically connected toan interconnection substrate forming an electronic package whereinperipheral non-bonded pads on the uppermost top chip of the assembly areelectrically connected to pads on the interconnection substrate with thestacked lower chip or chips of the assembly being enclosed in a cavityin the interconnection substrate with the solder connections between thestacked chips and cavity area being effectively sealed (encapsulated) toprovide mechanical, electrical and chemical reliability for theelectronic package.

[0013] It is another object of the present invention to provide a methodfor making an electronic component comprising a stacked integratedcircuit chip assembly comprising a plurality of electrically connectedchips electrically connected to a substrate, the component packagehaving enhanced electrical, mechanical and chemical reliabilityproperties wherein non-electrically connected peripheral pads on the topuppermost stacked chip of the assembly are electrically connected topads on the surface of the interconnection substrate by solderconnections with the lower chip or chips of the assembly being enclosedin a cavity in the substrate and the solder connections between thestacked chips and the cavity encapsulated with an encapsulant.

[0014] Still other objects and advantages of the invention will in partbe obvious and will in part be apparent from the specification.

SUMMARY OF THE INVENTION

[0015] In one aspect of the invention an electronic device is providedhaving enhanced mechanical, electrical and chemical reliabilitycomprising an assembly of a plurality of stacked electrically connectedintegrated circuit chips having a top chip and a bottom chip, the topchip having a larger width and length and a larger surface area than theother chips in the assembly and having peripheral non-bonded conductivepads thereon which peripheral pads are electrically connected tocorresponding conductive pads on the surface of an interconnectionsubstrate by solder connections between the corresponding sets of pads,the interconnection substrate having a cavity having an open areasmaller than the surface area of the top chip and an open area largerthan the other chips which cavity accommodates and encloses the bottomchip and other chips of the assembly other than the top chip and whereinthe cavity and solder connections between the chips are filled with anencapsulant by supplying an encapsulant material to the cavity through athrough opening in the substrate which communicates with the cavity, theopening extending from a surface of the substrate to the cavity.

[0016] In the method of the invention to make the electronic device, theencapsulant is typically heated and liquified and caused to flow throughthe opening into the cavity and the encapsulant flows into the cavityand spaces between the stacked chips and between a space between theperiphery of the top chip and the substrate surface preferablysubstantially filling the cavity and encapsulating all of the solderbump connections including the peripheral solder connections of the topchip providing a mechanically, electrically and chemically stabilizedand sealed stacked chip assembly containing electronic device.

[0017] In yet another aspect of the present invention, a method isprovided for making an electronic component comprising an assembly of aplurality of electrically connected stacked integrated circuit chips andan interconnection substrate, wherein peripheral conductive pads on atop chip of the stacked assembly are electrically connected tocorresponding pads on the surface of the interconnection substrate bysolder connections between their corresponding pairs of pads the methodcomprising the steps of:

[0018] providing an integrated circuit chip electrically connectedstacked assembly containing a plurality of chips wherein the top chip ofthe assembly contains peripheral pads which are electrically connectedto corresponding pads on the surface of an interconnection substrate bya plurality of solder connections forming a space between the padcontaining surface of the top chip and the pad containing surface of thesubstrate with the other chips of the stacked assembly being enclosed ina cavity in the substrate;

[0019] providing a fluid encapsulant; and

[0020] supplying the encapsulant to the cavity through a through openingin the substrate extending from a surface of the substrate andcommunicating with the cavity and sealing the cavity and encapsulatingthe solder connections between the stacked chips and the space betweenthe top chip and the interconnection substrate with the encapsulant.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The features of the invention believed to be novel and theelements characteristic of the invention are set forth withparticularity in the appended claims. The figures are for illustrationpurposes only and are not drawn to scale. The invention itself, however,both as to organization and method of operation, may best be understoodby reference to the detailed description which follows taken inconjunction with the accompanying drawings in which:

[0022]FIG. 1 is a cross-sectional view of an electronic componentcomprising a cavity containing substrate to which substrate a stackedchip assembly comprising a bottom chip and an electrically connectedlarger top chip is electrically attached, with the bottom chip enclosedwithin the cavity and peripheral pads on the top chip being electricallyconnected to the surface of the substrate and the cavity and electricalconnections sealed.

[0023]FIG. 2A is a side view of a stacked chip assembly as in FIG. 1ready for electrical attachment to a cavity containing substrate.

[0024]FIG. 2B is a side view of a stacked chip assembly comprising alarger chip electrically connected to an intermediate chip, whichintermediate chip is electrically connected to another chip.

[0025]FIG. 3 is a perspective view of an electronic component of theprior art comprising an integrated circuit chip containing pads andsolder bumps which chip is to be electrically joined to correspondingpads on a non-cavity interconnection substrate.

[0026]FIG. 4 is a cross-sectional view of FIG. 3 along lines 4-4 afterthe chip is joined to the substrate showing the chip and substrateelectrical interconnections being totally encapsulated.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

[0027] In describing the preferred embodiments of the present invention,reference will be made herein to FIGS. 1-4 of the drawings in which likenumerals refer to like features of the invention. Features of theinvention are not necessarily shown to scale in the drawings.

[0028] Referring first to FIGS. 3 and 4, a typical prior art non-cavityelectronic component 10 is shown comprising integrated circuit chip 11and interconnection substrate 15. Integrated circuit chip 11 is shownhaving conductive pads 12 overlaid with solder bumps 13. Correspondingconductive pads 14 are shown on substrate 15. Referring to FIG. 4,electronic component 10 is depicted in cross-section wherein integratedcircuit chip 11 is solder connected to interconnection substrate 15. Thechip 11 is electrically connected to the substrate 15 by a plurality ofsolder connections 13 such as solder bumps, in a method known as C4 orflip chip packaging. The lower surface of substrate 15 may containconnectors such as pin connectors 23 for connection of the substrate 15to another electronic device such as a circuit board.

[0029] The solder interconnections 13 of electronic component 10 asshown in FIG. 4 are encapsulated by a thermoplastic polymer or otherencapsulant 16 shown filling the space 19 between pad containing surface17 of chip 11 and pad containing surface 18 of substrate 15. Theencapsulant 16 is shown both around the periphery of chip 11 and underthe chip totally encapsulating all the solder bump 13 connections.

[0030]FIG. 1 shows a stacked chip assembly 25, as shown in FIG. 2A,electrically connected to a cavity containing substrate 20.

[0031] Referring to FIGS. 1 and 2A, the integrated circuit chips 26 and30 used to form the stacked assembly 25 may be any of a number ofintegrated circuit devices such as passive devices or a very large scaleintegration (VLSI) or ultra large scale integration (ULSI) activedevices. Exemplary devices are static random access memory (SRAM),dynamic (DRAM), microprocessor and ASIC chips and combinations thereof.

[0032] Interconnection substrate 20 is shown in FIG. 1 having a cavity21 and may be constructed of any number of suitable substrate materialssuch as ceramic or metal. Alumina, glass ceramic, and the like areexemplary. Interconnection substrate 20 is typically a multi-layersubstrate. It is preferable to use similar materials for both the chips30 and 26 of assembly 25 and substrate 20 to minimize thermal mismatchfor the formed electronic component and to enhance the integrity of thesolder bumps 32 bonding the chip assembly 25 to the substrate 20, whichbumps might otherwise be damaged due to thermal expansion when theelectronic component is on.

[0033] Chip assembly 25 is electrically connected to substrate 20 byflip chip C4 joining which involves aligning the pads 31 and solderbumps 32 of chip 26 of stacked assembly 25 with the pads 33 of substrate20 and then joining the chip 26 of the stacked assembly 25 and thesubstrate 20 by heating to melt the solder bumps 32 and forming anelectrical and mechanical connection between the chip 26 (and assembly25) and substrate 20. This process is usually called solder reflow.

[0034] Stacked chip assembly 25 as shown in FIG. 2A is first fabricatedbefore attachment to substrate 20 by solder bonding bottom chip 30 totop chip 26 by aligning pads 27 and 29 and solder bumps 28 and reflowingthe solder. This procedure is shown schematically in FIG. 3 where bumpcontaining pads on chip 11 are bonded to pads on substrate 15. In thiscase, the substrate 15 is chip 26. The stacked assembly 25 is thensolder joined to substrate 20 as described hereinabove.

[0035] As shown in FIG. 1, top chip 26 is larger (in width and lengthand surface area) than bottom chip 30 and overlies the periphery or sidewalls 21 b and 21 c of cavity 21. Chip 30 is shown surrounded andenclosed in cavity 21. Encapsulant 35 is shown being forced into cavity21 from dispenser 24 through inlet tube 24 a which extends into throughopening 22. Through opening 22 extends from surface 40 of substrate 20to wall 21 a into cavity 21. The encapsulant 35 fills the cavity 21 andthe space 41 between chip 30 and chip 26 and between the space 42between chip 26 and substrate 20. The encapsulant 35 is shown extendingto the periphery of chip 26.

[0036] Once the stacked chip assembly 25 has been electrically connectedto substrate 20, the substrate 20 can be electrically connected toanother electronic device by processes well known in the art such ascard join. This is accomplished by a variety of input/output methods.Pin grid arrays, such as 23 shown on FIG. 1, Ball grid arrays, wire orcast column arrays are all connection strategies to second levelpackaging which may be used.

[0037] The materials used for encapsulation may be high temperaturethermoplastic resins and may be selected from a number of resins havingthe properties necessary to provide the desired C4 encapsulation andmechanical, electrical and chemical reliability characteristics of theelectronic components of the invention. In general, the encapsulant mustnot degrade, have a suitable glass transition temperature and viscositycharacteristics for filling the cavity and be capable of reworking. Itis also important that the resins be soluble in solvents such asN-methylpyrolidone (NMP) for applying the resin to the C4 assembly andfor reworkability of the sealed C4 assembly. Other solvents includecommon aldehydes, ketones, tetrahydrofuran, HFIP andgamma-butyrolactone. An exemplary encapsulant is a modified epoxy.

[0038] Fillers have been used in encapsulants of the prior art to reduceand/or control the coefficient of thermal expansion or control the flowof the encapsulant during application and drying. This is important tominimize cracking or other problems caused by uneven thermal expansionof the chip, substrate, solder bump and encapsulant during use of theelectronic component and such fillers may be used in the presentinvention.

[0039] Filled resins may also be employed for special situations whereit is desired to, for example, control the viscosity of the resin duringthe encapsulation process. Any of the usual fillers may be used such assilica, ceramic, glass/ceramic, barium titanate, alumina, Kevlar, boron,carbon and PBI fibers in an amount typically of, by weight, about 0.1 to0.5% or more.

[0040] The encapsulation process is performed by melting or liquifyingthe encapsulant 35 and forcing the encapsulant into cavity 21 throughthrough opening 22 in substrate 20. A dispensing tool 24 having aninjection tube 24 a may be used to force the encapsulant into thecavity.

[0041] Referring again to FIG. 1, a through opening 22 is provided insubstrate 20 from the lower wall 21 a of cavity 21 to the surface 40 ofthe substrate. The through opening 22 preferably extends from the lowerwall 21 a of the cavity to the surface 40 of the substrate which surfaceis not being joined to the stacked chip assembly. A dispenser 24,preferably having a elongated tube 24 a, is inserted into opening 22 andis used to dispense a paste or encapsulant 35 into cavity 21. Thisprocess is performed after stack assembly chip 25 has been solderattached to substrate 20.

[0042] The through opening 22 is preferably positioned near (adjacent)the periphery or side walls 21 b or 21 c of cavity 21 and preferablyextends in a straight line from the surface 40 of the substrate to thecavity 21. The through opening 22 at this position has been found toallow capillary action to draw the encapsulant or underfill materialinto the spaces between the chips before the cavity is filled. Thethrough opening 22 may also be provided in cavity side walls 21 b or 21c or centrally in wall 21 a, however this is not as preferred as thethrough opening 22 at or near the periphery of cavity 21.

[0043] The use of a through opening 22 in substrate 20 has also beenfound to provide a number of other significant advantages forunderfilling a stacked chip assembly in a substrate having a cavity. Forone, the through opening 22 allows for the expansion of gases in thecavity during reflow without disturbing connections of the larger chip26 to the substrate 20. Typically, the space 42 between the chip and thesubstrate may be filled with flux and prevent gases from escaping andwithout the through hole, the expanded gases can force the chip off thesurface of the substrate during reflow and result in a poor ornon-existing connection.

[0044] For dispensing the underfill material 35, it is preferred thatthe substrate 22 be positioned with the cavity and connected chipassembly downward. Accordingly, as shown in FIG. 1, the chip assembly 25is placed downward with the substrate surface 40 being on top. This ispreferred so that the space between the chips and the C4 areas arefilled void free before the remainder of the larger volume cavity isfilled. As noted hereinabove, in a conventional process forencapsulating a single chip bonded to a substrate, the encapsulant wouldbe dispensed with the chip in an upward position. Using this typeprocess the encapsulant may wick between the large chip and thesubstrate but may also wick between the substrate and the small chipbefore the space between the chips is filled. This creates an air pocketwhich adversely affects the reliability of the connection.

[0045] Through opening 22 in substrate 20 may be formed in anyconvenient manner. It can be formed into the substrate prior to firing,but is preferred to be machined into the ceramic after firing. It canalso be ultrasonically machined in the ceramic after firing. Thediameter of the through opening 22 may vary widely and is typicallyabout 0.5 to 3 mm in diameter. A typical substrate 20 may range fromabout 21 mm wide to 64 mm on each side and 2 mm to 10 mm thick with thecavity opening about 5 mm to 22 mm on each side and 1 mm to 3 mm deep.The depth of cavity 21 (height of sidewalls 21 b and 21 c) and thelength of lower wall 21 a are sufficient to accommodate the stackedchips without contact with sidewalls 21 b or 21 c of lower wall 21 a andwill vary depending on the number of stacked chips in the stack chipassembly 25. Typically the cavity 21 will allow for about 0.25 mm to 1mm clearance between the sidewalls 21 b and 21 c of the cavity and thestacked chips and about 0.2 mm to 0.5 mm clearance between the lowerwall 21 a and the top of the stacked chip. The larger chip 26 which iselectronically attached to substrate 20 will overly the periphery of thecavity 21 and typically be about 2 mm to 10 mm larger than the openingof the cavity 21.

[0046] In FIGS. 1 and 2A only one chip 30 is shown stacked on largerchip 26 and accordingly the cavity is sized to fit the one chip 30. Aplurality of chips can be stacked on larger chip 26 as is known in theart. Such a stacked chip assembly is shown in FIG. 2B where another chip43 is electrically connected to chip 30 by pads 37 and 39 and solderbump 38.

[0047] Referring now to FIG. 2A, a stack chip assembly 25 is shown readyfor electrical connection to a substrate 20 as shown in FIG. 1. Thus, asmaller chip 30 is shown attached to a larger chip 26 by solderconnections 28 between bonding pads 27 of chip 26 and bonding pads 29 ofchip 30. Larger chip 26 has peripheral bonding pads 31 with solder bumps32 attached thereto. When chip assembly 25 is to be electricallyconnected to substrate 20, the solder bumps 32 of chip 26 are alignedwith pads 33 of substrate 20 and the solder reflowed joining chip 26 ofstack chip assembly 25 to substrate 20. The stacked chip-substrateassembly is then ready for underfill as shown in FIG. 1 using the methodof the invention as described hereinabove.

[0048] While the present invention has been particularly described, inconjunction with a specific preferred embodiment, it is evident thatmany alternatives, modifications and variations will be apparent tothose skilled in the art in light of the foregoing description. It istherefore contemplated that the appended claims will embrace any suchalternatives, modifications and variations as falling within the truescope and spirit of the present invention.

Thus, having described the invention, what is claimed is:
 1. Anelectronic device having enhanced mechanical, electrical and chemicalreliability comprising an assembly of a plurality of stackedelectrically connected integrated circuit chips having a top chip and abottom chip, the top chip having a larger width and length and a largersurface area than the other chips in the assembly and having peripheralnon-bonded conductive pads thereon which peripheral pads areelectrically connected to corresponding conductive pads on the surfaceof an interconnection substrate by solder connections between thecorresponding sets of pads, the interconnection substrate having acavity having an open area smaller than the surface area of the top chipand an open area larger than the other chips which cavity accommodatesand encloses the bottom chip and other chips of the assembly other thanthe top chip and wherein the cavity and solder connections between thechips and substrate are filled with an encapsulant by supplying anencapsulant material to the cavity through a through opening in thesubstrate which communicates with the cavity, the opening extending froma surface of the substrate to the cavity.
 2. The electronic device ofclaim 1 wherein the through opening extends from the bottom wall of thecavity to the interconnection substrate surface.
 3. The electronicdevice of claim 2 wherein the through opening is straight.
 4. Theelectronic device of claim 3 wherein the through opening is at or nearthe periphery of the cavity.
 5. The electronic device of claim 1 whereintwo or more stacked chips are electrically connected to the top chip. 6.A method for making an electronic component comprising an assembly of aplurality of electrically connected stacked integrated circuit chips andan interconnection substrate, wherein peripheral conductive pads on atop chip of the stacked assembly are electrically connected tocorresponding pads on the surface of the interconnection substrate bysolder connections between their corresponding pairs of pads the methodcomprising the steps of: providing an integrated circuit chipelectrically connected stacked assembly containing a plurality of chipswherein the top chip of the assembly contains peripheral pads which areelectrically connected to corresponding pads on the surface of aninterconnection substrate by a plurality of solder connections forming aspace between the pad containing surface of the top chip and the padcontaining surface of the substrate with the other chips of the stackedassembly being enclosed in a cavity in the substrate; providing a fluidencapsulant; and supplying the encapsulant to the cavity through athrough opening in the substrate extending from a surface of thesubstrate and communicating with the cavity and sealing the cavity andencapsulating the solder connections between the stacked chips and thespace between the top chip and the interconnection substrate with theencapsulant.
 7. The method of claim 6 wherein the through openingextends from the bottom wall of the cavity to the interconnectionsubstrate surface.
 8. The method of claim 7 wherein the through openingis straight.
 9. The method of claim 8 wherein the through opening is ator near the periphery of the cavity.
 10. The method of claim 6 whereintwo or more stacked chips are electrically connected to the top chip.